This invention relates generally to a circuit structure capable of active self-configuration to achieve wafer scale integration. More particularly the invention includes an integrated circuit wafer having plural unit circuits, together with functional testing and control means to configure functional circuits on the wafer.
It is well known in the manufacture of integrated circuit wafers, that as wafer size and complexity increase so also does the likelihood that manufacturing imperfections will appear in some of the chips on the wafer. Only one of the individual chips produced need be imperfect and malfunction to render an entire wafer inoperable as a single unit. In the prior art, all the chips on a wafer were tested, and those found to be functional were diced or separated out and repackaged. Then a series of such functional packages were interconnected to form a functional circuit. Various ways to circumvent or minimize the testing, dicing and repackaging steps, that is, to utilize the manufactured wafer as completely as possible without additional ancillary processing steps, became known as wafer scale integration. In so utilizing the manufactured wafer, it is highly desirable to minimize the processing steps required to make the wafer operational and at the same time to integrate, to the maximum possible extent, large scale portions of the wafer.
Prior art achieved wafer scale integration by a process called discretionary wiring. In discretionary wiring, the chips on a wafer are probed, tested, and the test results fed to a computer which determines an interconnect mask corresponding to a map of the functional chips on the wafer. Interconnection layers are then formed between functional chips using the computer-determined mask. Key drawbacks are the cost of the computer and the reprocessing system. Moreover, the interconnection is fixed and static; incapable of assimilating subsequent chip malfunctions.